H8SSLASH2214 datasheet(447/936 Pages) RENESAS

447 / 936 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 387 of 872

REJ09B0189-0400

10.2.9

Timer Synchro Register (TSYR)

—

SYNC0

R/W

SYNC2

R/W

SYNC1

R/W

Bit

Initial value

R/W

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channels 0 to 2 TCNT counters. A channel performs synchronous operation

when the corresponding bit in TSYR is set to 1.

TSYR is initialized to H'00 by a reset, and in hardware standby mode.

Bits 7 to 3—Reserved: Should always be written with 0.

Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, synchronous presetting of multiple channels*

1, and

synchronous clearing through counter clearing on another channel*

2 are possible.

Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

Bit n

SYNCn

Description

TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels)

(Initial value)

TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible

(n = 2 to 0)

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