H8SSLASH2214 datasheet(524/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 464 of 872

REJ09B0189-0400

12.2.6

Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

R/W

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in

module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE

Description

Transmit data empty interrupt (TXI) requests disabled*

(Initial value)

Transmit data empty interrupt (TXI) requests enabled

Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then

clearing it to 0, or clearing the TIE bit to 0.

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)

request and receive error interrupt (ERI) request generation when serial receive data is transferred

from RSR to RDR and the RDRF flag in SSR is set to 1.

Bit 6

RIE

Description

Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

disabled*

(Initial value)

Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

enabled

Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF

flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to

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