H8SSLASH2214 datasheet(583/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 523 of 872

REJ09B0189-0400

Thus the reception margin in asynchronous mode is given by formula (1) below.

M = | (0.5 –

) – (L – 0.5) F –

| D – 0.5 |

(1 + F) |

× 100%

........... Formula (1)

Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 16)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by

formula (2) below.

When D = 0.5 and F = 0,

M = (0.5 –

× 16

) × 100%

= 46.875%

........... Formula (2)

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

(8) Restrictions on Use of DMAC or DTC

(a) When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5

φ clock cycles after TDR is updated by the DMAC or DTC. Misoperation

may occur if the transmit clock is input within 4

φ clocks after TDR is updated. (Figure 12.27)

(b) When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant

SCI reception end interrupt (RXI).

0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the flags when

either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. In particular,

note that during transmission, data will not be transmitted correctly unless the CPU clears the

TDRE flag.

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