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H8S/2214 Scheda tecnica(PDF) 686 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 686 Page - Renesas Technology Corp |
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686 / 936 page ![]() Section 17 Power-Down Modes Rev.4.00 Sep. 18, 2008 Page 626 of 872 REJ09B0189-0400 (3) Clearing with the STBY Pin When the STBY pin is driven low, a transition is made to hardware standby mode. 17.5 Module Stop Mode 17.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 17.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules are retained. After reset release, all modules other than the DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. When a transition is made to sleep mode with all modules stopped (MSTPCR = H'FFFFFF), the bus controller and I/O ports also stop operating, enabling current dissipation to be further reduced. |
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