H8SSLASH2214 datasheet(690/936 Pages) RENESAS

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Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 630 of 872

REJ09B0189-0400

Table 17.4

Oscillation Stabilization Time Settings

STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz

6 MHz

4 MHz

2 MHz

Unit

8192 states

0.51

0.63

0.82

1.0

1.4

2.0

4.1

16384 states

1.0

1.3

1.6

2.0

2.7

4.1

8.2

32768 states

2.0

2.5

3.3

4.1

5.5

8.2

16.4

65536 states

4.1

5.0

6.6

8.2

10.9

16.4

32.8

131072 states

8.2

10.1

13.1

16.4

21.8

32.8

65.5

262144 states

16.4

20.2

26.2

32.8

43.7

65.5

131.1

2048 states

0.13

0.16

0.20

0.26

0.34

0.51

1.0

16 states

1.0

1.2

1.6

2.0

2.7

4.0

8.0

µs

: Recommended time setting

(2) Using an External Clock

Any value can be set. Normally, use of the minimum time is recommended.

Note:

In the F-ZTAT version, a 16-state standby time cannot be used with an external clock. Use

2048 states or more.

17.6.4

Software Standby Mode Application Example

Figure 17.3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

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