H8SSLASH2214 datasheet(688/936 Pages) RENESAS

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Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 628 of 872

REJ09B0189-0400

17.5.2

Usage Notes

(1) DMAC and DTC Module Stop Mode

Depending on the operating status of the DMAC and DTC, the MSTPA7 and MSTPA6 bits may

not be set to 1. Setting of the DTC module stop mode should be carried out only when the DTC is

not activated.

For details, section 7, DMA Controller (DMAC) and section 8, Data Transfer Controller (DTC).

(2) On-Chip Supporting Module Interrupts

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module

stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU

interrupt source, DMAC, or DTC activation source. Interrupts should therefore be disabled before

setting module stop mode.

(3) Writing to MSTPCR

MSTPCR should be written to only by the CPU.

17.6

Software Standby Mode

17.6.1

Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in

software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and

oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states

of on-chip supporting module, and of the I/O ports, are retained. The address bus and bus control

signals are placed in the high-impedance state.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

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