H8SSLASH2214 datasheet(689/936 Pages) RENESAS

689 / 936 page

Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 629 of 872

REJ09B0189-0400

17.6.2

Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins

IRQ0 to IRQ7), or by

means of the

RES pin, MRES pin or STBY pin.

(1) Clearing with an Interrupt

When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after

the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire

H8S/2214 chip, software standby mode is cleared, and interrupt exception handling is started.

When software standby mode is cleared with an IRQ0 to IRQ7 interrupt, set the corresponding

enable bit to 1 and ensure that an interrupt of higher priority than interrupts IRQ0 to IRQ7 is not

generated. Software standby mode cannot be cleared if the interrupt has been masked by the CPU

side or has been designated as a DTC activation source.

(2) Clearing with the

RES Pin and MRES Pin

When the

RES pin and MRES pin are driven low, clock oscillation is started. At the same time as

clock oscillation starts, clocks are supplied to the entire H8S/2214 chip. Note that the

RES pin and

MRES pin must be held low until clock oscillation stabilizes. When the RES pin and MRES pin

go high, the CPU begins reset exception handling.

(3) Clearing with the

STBY Pin

When the

STBY pin is driven low, a transition is made to hardware standby mode.

17.6.3

Setting Oscillation Stabilization Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

(1) Using a Crystal Oscillator

Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time).

Table 17.4 shows the standby times for different operating frequencies and settings of bits STS2 to

STS0.

H8S/2214 Scheda tecnica(PDF) 689 Page - Renesas Technology Corp