H8SSLASH2214 datasheet(693/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 633 of 872

REJ09B0189-0400

Oscillator

RES

STBY

Oscillation

stabilization

time (tOSC1)

Reset exception

handling

Figure 17.4 Hardware Standby Mode Timing (Example)

17.8

φ Clock Output Disabling Function

Output of the

φ clock can be controlled by means of the PSTOP bit in SCKCR and the

corresponding DDR bit. When the PSTOP bit is set to 1, the

φ clock is stopped at the end of the

bus cycle, and

φ output goes high. φ clock output is enabled when PSTOP bit is cleared to 0. When

DDR for the corresponding port is cleared to 0,

φ clock output is disabled and input port mode is

set. Table 17.5 shows the state of the

φ pin in each processing mode.

Table 17.5

φ Pin State in Each Processing Mode

DDR

PSTOP

—

Hardware standby mode

High impedance

High impedance High impedance

Software standby mode

High impedance

Fixed high

Sleep mode

High impedance

φ output

Fixed high

High-speed mode, medium-speed mode

High impedance

φ output

Fixed high

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