H8SSLASH2214 datasheet(692/936 Pages) RENESAS

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Section 17 Power-Down Modes

Rev.4.00 Sep. 18, 2008 Page 632 of 872

REJ09B0189-0400

17.7

Hardware Standby Mode

17.7.1

Hardware Standby Mode

When the

STBY pin is driven low, a transition is made to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the

STBY pin low.

Do not change the state of the mode pins (MD2 to MD0) while the H8S/2214 is in hardware

standby mode.

Hardware standby mode is cleared by means of the

STBY pin and the RES pin. When the STBY

pin is driven high while the

RES pin is low, the reset state is set and clock oscillation is started.

Ensure that the

RES pin is held low until the clock oscillation stabilizes (at least t

osc1 —the

oscillation stabilization time—when using a crystal oscillator). When the

RES pin is subsequently

driven high, a transition is made to the program execution state via the reset exception handling

state.

17.7.2

Hardware Standby Mode Timing

Figure 17.4 shows an example of hardware standby mode timing.

When the

STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the

STBY pin high, waiting

for the oscillation stabilization time, then changing the

RES pin from low to high.

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