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H8S/2214 Scheda tecnica(PDF) 809 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 809 Page - Renesas Technology Corp |
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809 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 749 of 872 REJ09B0189-0400 SYSCR—System Control Register H'FDE5 MCU 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 0 RAME 1 R/W 2 MRESE 0 R/W 1 — 0 — Bit Initial value R/W : : : RAM Enable 0 1 On-chip RAM is disabled On-chip RAM is enabled Manual Reset Select Bit 0 1 Manual reset is disabled Manual reset is enabled NMI Interrupt Input Edge Select 0 1 Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input Interrupt Control Mode Select 0 1 0 1 0 1 Interrupt control mode 0 Interrupts controlled by I bit Setting prohibited Interrupt control mode 2 Interrupts controlled by bits I2 to I0, and IPR Setting prohibited Reserved Only 0 should be written to this bit. |
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