H8SSLASH2214 datasheet(857/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 797 of 872

REJ09B0189-0400

DMAWER—DMA Write Enable Register

H'FF60

DMAC

—

WE1B

R/W

WE0A

R/W

WE1A

R/W

WE0B

R/W

Write Enable 1A

Disables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and

DMATCR bit 5

Enables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and

DMATCR bit 5

Disables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2

Enables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2

Disables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0

Enables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0

Write Enable 0B

Disables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and

DMATCR bit 4

Enables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and

DMATCR bit 4

Write Enable 0A

Write Enable 1B

Bit

Initial value

R/W

DMATCR—DMA Terminal Control Register

H'FF61

DMAC

—

TEE1

R/W

TEE0

R/W

—

Bit

Initial value

R/W

Disables

TEND1 pin output

Enables

TEND1 pin output

Transfer End Pin Enable 1

Disables

TEND0 pin output

Enables

TEND0 pin output

Transfer End Pin Enable 0

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