H8SSLASH2214 datasheet(142/936 Pages) RENESAS

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Section 4 Exception Handling

Rev.4.00 Sep. 18, 2008 Page 82 of 872

REJ09B0189-0400

4.2

Reset

4.2.1

Overview

A reset has the highest exception priority.

When the

RES or MRES pin goes low, all processing halts and the H8S/2214 enters the reset state.

A reset initializes the internal state of the CPU and the registers of on-chip supporting modules.

Immediately after a reset, interrupt control mode 0 is set.

Reset exception handling begins when the

RES or MRES pin changes from low to high.

The levels of the

RES and MRES pins at reset determine whether a power-on reset or a manual

reset is effected.

The H8S/2214 can also be reset by overflow of the watchdog timer. For details see section 11,

Watchdog Timer (WDT).

4.2.2

Reset Types

A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in

table 4.3. A power-on reset should be used when powering on.

The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes

all the registers in the on-chip supporting modules, while a manual reset initializes all the registers

in the on-chip supporting modules except for the bus controller and I/O ports, which retain their

previous states.

With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip

supporting module I/O pins are switched to I/O ports controlled by DDR and DR.

Table 4.3

Reset Types

Reset Transition

Conditions

Internal State

Type

MRES

RES

CPU

On-Chip Supporting Modules

Power-on reset

Low

Initialized

Manual reset

Low

High

Initialized

Initialized, except for bus controller

and I/O ports

*: Don’t care

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