H8SSLASH2224 datasheet(330/1071 Pages) RENESAS

330 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 244 of 982

REJ09B0054-0500

8.5.5

Single Address Mode

DMAC supports the dual address mode, in which two different cycles are used for reading and

writing, and the single address mode, in which a single cycle is used for both reading and writing.

In dual address mode, the source address and the destination address are specified respectively for

transferring data.

In single address mode, data is transferred between the external space, in which the transfer source

or transfer destination is specified by the address, and the external device that is selected by

DACK strobe regardless of the address. Figure 8.9 shows the data bus in single address mode.

HWR, LWR

A23 to A0

Address bus

External

memory

External

device

(Write)

(Read)

D15 to D0

(High impedance)

This LSI

DACK

Figure 8.9 Data Bus in Single Address Mode

When the data bus is used for reading in single address mode, data is transferred from the external

memory to the external device and the

DACK pin functions as the write strobe for the external

device. When the data bus is used for writing in single address mode, data is transferred from the

external device to the external memory and the

DACK pin functions as the read strobe for the

external device. Since the direction for the external device cannot be controlled, chose one of

directions described above.

The setting of the bus controller for the external memory area controls the bus cycle in single

address mode. To the external device,

DACK is output in synchronization with the address strobe.

For details on the bus cycle, see section 8.5.10, DMA Transfer (Single Address Mode) Bus

Cycles.

In single address mode, do not specify the internal area for the transfer address.

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