H8SSLASH2224 datasheet(334/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 248 of 982

REJ09B0054-0500

8.5.6

Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode

can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in

DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response

to a single transfer request, and this is executed the number of times specified in ETCRA. The

transfer source is specified by MARA, and the transfer destination by MARB. Table 8.9

summarizes register functions in normal mode.

Table 8.9

Function

Initial Setting

Operation

MARA

Source address

Start address of

transfer source

Incremented/decremented

every transfer, or fixed

MARB

Destination

address register

Start address of

transfer destination

Incremented/decremented

every transfer, or fixed

ETCRA

Transfer counter Number of transfers Decremented every

transfer; transfer ends

when count reaches

H'0000

MARA and MARB specify the start addresses of the transfer source and transfer destination,

respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or

word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be

set separately for MARA and MARB.

The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time

a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared

and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent

to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

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