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H8S/2224 Scheda tecnica(PDF) 337 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 337 Page - Renesas Technology Corp |
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337 / 1071 page ![]() Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 251 of 982 REJ09B0054-0500 8.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 8.10 summarizes register functions in block transfer mode. Table 8.10 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed 0 ETCRAH 7 Holds block size Block size Fixed 0 ETCRAL 7 Block size counter Block size Decremented every transfer; ETCRH value copied when count reaches H'00 15 0 ETCRB Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 8.14 illustrates operation in block transfer mode when MARB is designated as a block area. |
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