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H8S/2224 Scheda tecnica(PDF) 338 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 338 Page - Renesas Technology Corp |
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338 / 1071 page ![]() Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 252 of 982 REJ09B0054-0500 Address T A Address B A Transfer Address T B Address B B 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Legend: Address Address Address Address Where : = L A = L B = L A + SAIDE ( 1)SAID (2DTSZ (M N 1)) = L B + DAIDE ( 1)DAID (2DTSZ (N 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL T A T B B A B B L A L B N M Figure 8.14 Operation in Block Transfer Mode (BLKDIR = 0) |
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