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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 342 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 342 Page - Renesas Technology Corp |
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342 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 256 of 982 REJ09B0054-0500 8.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. φ Address bus DMAC cycle (1-word transfer) RD LWR HWR Source address Destination address CPU cycle CPU cycle T 1 T 2 T 3 T 1 T 2 T 3 T 1 T 2 Figure 8.18 Example of DMA Transfer Bus Timing |
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