H8SSLASH2224 datasheet(343/1071 Pages) RENESAS

343 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 257 of 982

REJ09B0054-0500

8.5.9

DMA Transfer (Dual Address Mode) Bus Cycles

Short Address Mode: Figure 8.19 shows a transfer example in which

TEND output is enabled

and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external

8-bit, 2-state access space to internal I/O space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release

Last transfer

cycle

DMA

write

DMA

dead

DMA

read

DMA

write

DMA

read

DMA

write

Bus release

Bus

release

Figure 8.19 Example of Short Address Mode Transfer

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when

TEND output is enabled, TEND output goes low in the transfer end cycle.

Full Address Mode (Cycle Steal Mode): Figure 8.20 shows a transfer example in which

TEND

output is enabled and word-size full address mode transfer (cycle steal mode) is performed from

external 16-bit, 2-state access space to external 16-bit, 2-state access space.

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