H8SSLASH2224 datasheet(346/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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346 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 260 of 982

REJ09B0054-0500

DMA

read

Address bus

LWR

TEND

HWR

Bus release

Block transfer

Last block transfer

DMA

write

DMA

read

DMA

write

DMA

dead

DMA

read

DMA

write

DMA

read

DMA

write

DMA

dead

Bus

release

Bus release

Figure 8.22 Example of Full Address Mode Transfer (Block Transfer Mode)

A one-block transfer is performed for a single transfer request, and after the transfer the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-

state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated

during data transfer, block transfer operation is not affected until data transfer for one block has

ended.

DREQ

DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel

for which the

DREQ pin is selected.

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