H8SSLASH2224 datasheet(347/1071 Pages) RENESAS

347 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 261 of 982

REJ09B0054-0500

Figure 8.23 shows an example of normal mode transfer activated by the

DREQ pin falling edge.

DMA

read

Address

bus

DREQ

Idle

Write

Idle

Bus release

DMA

control

Channel

Write

Idle

Transfer source

Request

[1]

[3]

[2]

[4]

[6]

[5]

[7]

Acceptance resumes

DMA

write

Bus

release

DMA

read

DMA

write

Bus

release

Request

Transfer destination

Transfer source

Transfer destination

Read

Request clear period

Minimum

of 2 cycles

Minimum

of 2 cycles

[1]

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] Start of DMA cycle;

DREQ pin high level sampling on the rising edge of φ starts.

[4] [7] When the

DREQ pin high level has been sampled, acceptance is resumed after the write cycle

is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 8.23 Example of

DREQ

DREQ Pin Falling Edge Activated Normal Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared, and

DREQ pin high level sampling for edge detection is started. If DREQ pin

high level sampling has been completed by the time the DMA write cycle ends, acceptance

resumes after the end of the write cycle,

DREQ pin low level sampling is performed again, and

this operation is repeated until the transfer ends.

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