H8SSLASH2224 datasheet(350/1071 Pages) RENESAS

350 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 264 of 982

REJ09B0054-0500

Figure 8.26 shows an example of block transfer mode transfer activated by

DREQ pin low level.

DMA

read

DMA

write

Address

bus

DREQ

Idle

Write

Bus release

DMA

control

Channel

Write

Transfer source

Request

[1]

[3]

[2]

[4]

[6]

[5]

[7]

Acceptance resumes

DMA

dead

Bus

release

DMA

read

DMA

write

DMA

dead

Bus

release

1 block transfer

Idle

Dead

1 block transfer

Acceptance resumes

Request

Minimum

of 2 cycles

Minimum

of 2 cycles

Transfer source

Read

Request clear period

Read

Request clear period

Transfer destination

Idle

[1]

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMA cycle is started.

[4] [7] Acceptance is resumed after the dead cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 8.26 Example of

DREQ

DREQ Pin Low Level Activated Block Transfer Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared. After the end of the dead cycle, acceptance resumes,

DREQ pin low level

sampling is performed again, and this operation is repeated until the transfer ends.

H8S/2224 Scheda tecnica(PDF) 350 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 350 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL