H8SSLASH2224 datasheet(354/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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354 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 268 of 982

REJ09B0054-0500

Figure 8.30 shows a transfer example in which

TEND output is enabled and word-size single

address mode transfer (write) is performed from an external device to external 8-bit, 2-state access

space.

DMA write

Address bus

DMA write

DMA

dead

HWR

TEND

DACK

Bus

release

LWR

Bus

release

Bus

release

Bus

release

Last transfer

cycle

Figure 8.30 Example of Single Address Mode Transfer (Word Write)

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

DREQ

DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel

for which the

DREQ pin is selected.

H8S/2224 Scheda tecnica(PDF) 354 Page - Renesas Technology Corp