H8SSLASH2224 datasheet(440/1071 Pages) RENESAS

440 / 1071 page

Section 10 I/O Ports

Rev. 5.00 Aug 08, 2006 page 354 of 982

REJ09B0054-0500

• PF0/BREQ/IRQ2

The pin functions are switched as shown below according to the combination of operating

mode, the BRLE bit, and the PF0DDR bit.

Operating mode

Modes 4 to 6

Mode 7

BRLE



PF0DDR



Pin functions

PF0 input pin

PF0 output

BREQ input

PF0 input pin

PF0 output

IRQ2 input pin*

Note:

* When this pin is used as an external interrupt pin, do not specify other functions.

10.12 Port G

Port G is a 5-bit I/O port and has the following registers.

• Port G data direction register (PGDDR)

• Port G data register (PGDR)

• Port G register (PORTG)

10.12.1 Port G Data Direction Register (PGDDR)

PGDDR specifies input or output of the port G pins using the individual bits. PGDDR cannot be

read; if it is, an undefined value will be read. This register is a write-only register, and cannot be

written by bit manipulation instruction. For details, see section 2.9.4, Access Methods for

Registers with Write-Only Bits.

Bit

Bit Name

Initial

Value

R/W

Description

7 to



Undefined



Reserved

These bits are always read as undefined value.

PG4DDR

0/1*

PG3DDR

PG2DDR

PG1DDR

PG0DDR

When a pin is specified as a general purpose I/O port,

setting this bit to 1 makes the corresponding port G

pin an output port. Clearing this bit to 0 makes the pin

an input port.

Note:

* In modes 4 and 5, initial value is 1. In modes 6 and 7, initial value is 0.

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