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H8S/2224 Scheda tecnica(PDF) 546 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 546 Page - Renesas Technology Corp |
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546 / 1071 page ![]() Section 12 8-Bit Timers Rev. 5.00 Aug 08, 2006 page 460 of 982 REJ09B0054-0500 φ Address TCNT address Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle by CPU Counter write data Figure 12.11 Contention between TCNT Write and Increment 12.8.3 Contention between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 12.12 shows this operation. φ Address TCOR address Internal write signal TCNT TCOR NM T1 T2 TCOR write cycle by CPU TCOR write data N N + 1 Compare-match signal Prohibited Figure 12.12 Contention between TCOR Write and Compare-Match |
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