H8SSLASH2224 datasheet(549/1071 Pages) RENESAS

549 / 1071 page

Section 12 8-Bit Timers

Rev. 5.00 Aug 08, 2006 page 463 of 982

REJ09B0054-0500

No.

Timing of Switchover by Means

of CKS1 and CKS0 Bits

TCNT Clock Operation

Switching from high to low*

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1

N + 2

Switching from high to high

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1

N + 2

Notes: 1. Includes switching from low to stop, and from stop to low.

2. Includes switching from stop to high.

3. Includes switching from high to stop.

4. Generated on the assumption that the switchover is a falling edge; TCNT is

incremented.

12.8.6

Contention between Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be

disabled before entering module stop mode.

12.8.7

Mode Setting of Cascaded Connection

When the 16-bit count mode and the compare-match count mode are set at the same time, input

clocks for TCNT_0 and TCNT_1 (TCNT_2 and TCNT_3)* are not generated and the timer stops

incrementation. This setting is prohibited.

Note: * Not available in the H8S/2237 Group and H8S/2227 Group.

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