H8SSLASH2224 datasheet(582/1071 Pages) RENESAS

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 496 of 982

REJ09B0054-0500

in a single communications frame, the slave unit is unlocked by the master unit. In this case, a

bit (bit 2) relevant to lock in the byte indicating the slave status is cleared to 0.

Note that locking and unlocking are not performed in broadcast communications.

Note: * There are three methods to unlock by a locked unit itself.

• Perform hardware reset

• Enter module stop mode

• Issue unlock command by the IEBus command register (IECMR)

Note that the LCK flag in IEFLG can be used to check whether the unit is

locked/unlocked.

14.1.4

Bit Format

Figure 14.5 shows the bit format (conceptual diagram) configuring the IEBus communications

frame.

Logic 1

Logic 0

Active low: Logic 1 = low level and logic 0 = high level

Active high: Logic 1 = high level and logic 0 = low level

Preparation

period

Synchronous

period

Data

period

Halt

period

Figure 14.5 IEBus Bit Format (Conceptual Diagram)

Each period of bit format for use of active high signals is described below.

• Preparation period: first logic 1 period (high level)

• Synchronous period: subsequent logic 0 period (low level)

• Data period: period indicating bit value (logic 1: high level, logic 0: low level)

• Halt period: last logic 1 cycle (high level)

For use of active low signals, levels are reversed from the active high signals.

The synchronous and data periods have approximately the same length.

The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods

allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit).

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