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H8S/2224 Scheda tecnica(PDF) 593 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 593 Page - Renesas Technology Corp

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 5.00 Aug 08, 2006 page 507 of 982
REJ09B0054-0500
14.3.9
IEBus Transmit Buffer Register (IETBR)
IETBR is a 1-byte buffer to which data to be transmitted in master or slave transmission is written.
IETBR is empty when the TxRDY flag in IETSR is 1. Check the TxRDY flag before setting
transmit data in IETBR.
Data written in IETBR is transmitted in the data field in master or slave transmission. Figure 14.6
shows the correspondence between the communications signal format and registers for IEBus data
transfer.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
TBR7
TBR6
TBR5
TBR4
TBR3
TBR2
TBR1
TBR0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data to be transmitted is written to this 1-byte
buffer.
IETBFL
[In master transmission]
[In slave transmission]
Communications frame
Communications frame
Register
Register
Notes: 1. In slave transmission, the received master address is not saved. If the unit is locked,
address comparison performed.
2. The received slave address is compared with IEAR1 and IEAR2, and if these addresses
match, operation continues.
3. In slave transmission, the received control bits are not saved. The received control bits
are decoded to decide the subsequent operation.
IETBR
Message length
bits
Data bits
Slave address
Master address
Control bits
Message length
bits
Data bits
Slave address
Master address
Control bits
IESA1, IESA2
IEAR1, IEAR2
CTL3 to CTL0
in IEMCR
(*1)
(*3)
(*2)
IEAR1, IEAR2
IETBFL
IETBR
Figure 14.6 Transmission Signal Format and Registers in Data Transfer



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