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H8S/2224 Scheda tecnica(PDF) 597 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 597 Page - Renesas Technology Corp

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 5.00 Aug 08, 2006 page 511 of 982
REJ09B0054-0500
14.3.15 IEBus Lock Address Register 1 (IELA1)
IELA1 specifies the lower 8 bits of a locked address when a unit is locked. Data in this register is
valid when the LCK flag in IEFLG is set to 1. This register cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
ILA7
ILA6
ILA5
ILA4
ILA3
ILA2
ILA1
ILA0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Lower 8 Bits of IEBus Lock Address
Store the lower 8 bits of the master unit address
when a unit is locked.
14.3.16 IEBus Lock Address Register 2 (IELA2)
IELA2 is an 8-bit read-only register that specifies the upper 4 bits of a locked address when a unit
is locked. Data in this register is valid when the LCK flag in IEFLG is set to 1. This register
cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
All 0
R
Reserved
These bits are always read as 0.
3
2
1
0
ILA11
ILA10
ILA9
ILA8
0
0
0
0
R
R
R
R
Upper 4 Bits of IEBus Locked Address
Store the upper 4 bits of the master unit address
when a unit is locked.



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