H8SSLASH2224 datasheet(594/1071 Pages) RENESAS

594 / 1071 page

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 508 of 982

REJ09B0054-0500

14.3.10 IEBus Reception Master Address Register 1 (IEMA1)

IEMA1 indicates the lower four bits of the communications destination master unit address in

slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the

contents are changed at the timing of setting the RxS flag in IERSR.

If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is

not in the receive enabled state on control field reception, a receive error interrupt is generated and

the lower 4 bits of the master address are stored in IEMA1. This register cannot be modified.

Bit

Bit Name

Initial Value

R/W

Description

IMA3

IMA2

IMA1

IMA0

Lower 4 Bits of IEBus Reception Master Address

Indicate the lower 4 bits of the communications

destination master unit address in slave/broadcast

reception.

3 to 0



All 0

Reserved

These bits are always read as 0.

14.3.11 IEBus Reception Master Address Register 2 (IEMA2)

IEMA2 indicates the upper 8 bits of the communications destination master unit address in

slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the

contents are changed at the timing of setting the RxS flag in IERSR.

If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer

is not in the receive enabled state at control field reception, a receive error interrupt is generated

and the upper 8 bits of the master address are stored in IEMA2. This register cannot be modified

by a write.

Bit

Bit Name

Initial Value

R/W

Description

IMA11

IMA10

IMA9

IMA8

IMA7

IMA6

IMA5

IMA4

Upper 8 Bits of IEBus Reception Master Address

Indicate the upper 8 bits of the communications

destination master unit address in slave/broadcast

reception.

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