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H8S/2224 Scheda tecnica(PDF) 596 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 596 Page - Renesas Technology Corp

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 5.00 Aug 08, 2006 page 510 of 982
REJ09B0054-0500
14.3.14 IEBus Receive Buffer Register (IERBR)
IERBR is a 1-byte read-only buffer that stores data received in master or slave reception. This
register can be read when the RxRDY flag in IERSR is set to 1. This register indicates the data
field value both in master and slave receptions. This register cannot be modified.
Figure 14.7 shows the relationship between transmission signal format and registers in IEBus data
reception.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
RBR0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
One-byte read-only buffer that stores data received
in master or slave reception
IEMA1, IEMA2 IEAR1, IEAR2
IERCTL
IERBFL
IERBR
(*)
IEAR1, IEAR2
IESA1, IESA2
IERBFL
IERBR
[In slave reception]
[In master reception]
Communications frame
Communications frame
Register
Note: * Received slave address is compared with IEAR1 and IEAR2. If they match,
the following operations are performed.
Register settings
Message length
bits
Data bits
Slave address
Master address
Control bits
Message length
bits
CTL3 to CTL0
in IEMCR
Data bits
Slave address
Master address
Control bits
Figure 14.7 Relationship between Transmission Signal Format and Registers
in IEBus Data Reception



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