H8SSLASH2224 datasheet(614/1071 Pages) RENESAS

614 / 1071 page

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 528 of 982

REJ09B0054-0500

Because the TxRDY flag is retained after a reset, the DTC transfer starts when the IETxI is

enabled and the first data for the data field is written to IETBR. The DTC negates the TxRDY

flag and the first byte of DTC transfer is completed.

(3) Master Transmission Flow

Figure 14.8 shows the master transmission flow. Numbers in the following description correspond

to the number in figure 14.8.

1. After the IEB and DTC have been initialized, a master communications request command is

issued from IECMR. During slave reception, the command execution status flag (CMX) in

IEFLG is set and the master communications request will not be issued.

2. When the slave reception has been completed, the CMX flag is cleared, the master

communications command is executed, and the MRQ flag is set.

3. The transmit start detection flag (TxS) in IETSR is set when arbitration is won and the master

address has been transmitted. In this case, one of the transmit status interrupts (IETSI) is

requested to the CPU, and the TxS flag is cleared in the interrupt handling routine.

4. The IEB loads data to be transmitted in the data field from IETBR when the control and

message length fields have been transmitted and an ACK is received in each field. After that,

the TxRDY flag is set. A DTC transfer request is generated by IETxI and the second byte is

written to the transmit buffer.

5. Similarly, the data field load and transmission are repeated.

6. The DTC completes the data transfer for the number of specified bytes when data to be

transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.

It, however, clears bit DTCEG5 in the DTC enable register G (DTCERG) so as not to generate

more DTC transfer request.

7. A TxRDY interrupt (IETxI) is issued to the CPU when the DTC transfer is completed. In this

interrupt handling routine, the TxRDY flag can be cleared. However, since a TxRDY interrupt

will be generated again after the last byte transfer, the TxRDY flag remains set. (Note that the

LUEE bit must be cleared to 0 because an underrun error occurs to terminate the transfer if the

LUEE bit in IECTR is set to 1.) Note, however, that the TxRDY interrupt must be disabled

because the TxRDY interrupt is always generated.

8. A transmit normal completion (TxF) interrupt (IETSI) occurs after the last data transfer is

completed. In this case, the CPU clears the TxF flag and completes the normal completion

interrupt and clears the MRQ flag to 0.

Note: As a transmit status interrupt (IETSI), the transmit error termination (TxE) interrupt as

well as the transfer start detection (TxS) and transmit normal completion (TxF) interrupts

must be enabled. If an error termination interrupt is disabled, no interrupt is generated

even if the transmission is terminated by an error.

H8S/2224 Scheda tecnica(PDF) 614 Page - Renesas Technology Corp