H8SSLASH2224 datasheet(617/1071 Pages) RENESAS

617 / 1071 page

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 531 of 982

REJ09B0054-0500

3. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI

occurs, and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the

RxRDY flag.

4. Similarly, the data field reception and load are repeated.

5. When the last data is received, the DTC completes the data transfer for the specified number of

bytes after loading the receive data to the RAM. In this case, the DTC does not clear the

RxRDY flag. It, however, clears the DTC enable register G (DTCEG). Accordingly, hereafter,

no transfer request will be issued to the DTC.

6. When the DTC transfer has been completed, an RxRDY interrupt (IERxI) is issued to the

CPU. In this interrupt handling routine, the RxRDY flag is cleared.

7. When the last data is received, a receive normal completion (RxF) interrupt (IERSI) occurs. In

this case, the CPU clears the RxF flag in order to complete the normal completion interrupt.

The SRE flag is cleared to 0.

Notes: 1. As a receive status interrupt (IERSI), the receive error termination (RxE) interrupt as

well as the receive start detection (RxS) and receive normal completion (RxF)

interrupts must be enabled. If an error termination interrupt is disabled, no interrupt is

generated even if the reception is terminated by an error.

2. The interrupt occurs after the DTC transfer has been completed. Accordingly, the

interrupt described in item 6 actually occurs after item 7 above.

H8S/2224 Scheda tecnica(PDF) 617 Page - Renesas Technology Corp