H8SSLASH2224 datasheet(616/1071 Pages) RENESAS

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 530 of 982

REJ09B0054-0500

The above registers can be specified in any order. (The register specification order does not affect

the IEB operation.)

(2) DTC Initialization

1. Set the start address of the RAM which stores the register information necessary for the DTC

transfer in the vector address (H'000004D2) to be accessed when a DTC transfer request is

generated.

2. Specify the following from the start address of the RAM.

 Transfer source address (SAR): Address (H'FFF80D) of the IEBus receive buffer register

(IERBR).

 Transfer destination address (DAR): Start address of the RAM which stores data received

from the data field.

 Transfer count (CRA): Maximum number of transfer bytes in one frame in the transfer

mode.

3. Set DTCEG6 in the DTC enabler register G (DTCERG) to enable the RxRDY interrupt

(IETxI).

Because the above settings are performed before the frame reception, the length of data to be

received cannot be decided. Accordingly, the maximum number of transfer bytes in one frame is

specified as the DTC transfer count.

If the DTC is specified after reception starts, the above settings are performed in the receive start

(RxS) interrupt handling routine. In this case, the transfer count must be the same value as the

contents of the IEBus receive message length register (IERBFL).

(3) Slave Reception Flow

Figure 14.9 shows the slave reception flow. Numbers in the following description correspond to

the number in figure 14.9. In this example, the DTC is specified when the frame reception starts.

1. After the broadcast reception has been completed, the slave reception is performed. The

receive broadcast bit status flag (RSS) in IEFLG retains the previous frame information (set to

1) until the receive start detection flag (RxS) is set to 1. If the RSS flag changes at the timing

of header reception, the interrupt handling of the broadcast reception completion must be

completed before the header reception. Accordingly, the RSS flag is stipulated that it changes

at the timing of starting reception.

2. If data is received up to the message length field, a receive start detection (RxS) interrupt

(receive status interrupt (IERSI)) will occur and the SRE flag is set to 1. In this case, the DTC

initialization described in (2) is performed. After initialization, the RxS flag is cleared to 0.

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