H8SSLASH2224 datasheet(621/1071 Pages) RENESAS

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 535 of 982

REJ09B0054-0500

(3) Master Reception Flow

Figure 14.11 shows the master reception flow. Numbers in the following description correspond to

the number in figure 14.11. In this example, the DTC is specified when the frame reception starts.

1. After the IEB has been initialized, a master communications request command is issued from

IECMR. During slave reception, the command execution status flag (CMX) in IEFLG is set

and the master communications request will not be issued.

2. The CMX flag is cleared when the slave reception is completed, the master communications

command is executed, and the MRQ flag is set.

3. If the arbitration is won, the master address, slave address, and control field will be

transmitted. An error generated before the control field transmission will be handled as a

transmission error. In this case, the TxE flag is set and the error contents will be reflected in

IETEF.

4. The message length field is received from the slave unit. If no parity error is detected and

reception is performed correctly, the receive start detection flag (RxS) is set to 1. If a parity

error occurs, it is handled as a receive error. A receive start detection (RxS) interrupt (receive

status interrupt (IERSI)) occurs and the DTC initialization described in (2) is performed. After

DTC initialization, the RxS flag is cleared to 0.

5. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI

occurs and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the

RxRDY flag.

6. Similarly, the above data field receive and load operations are repeated.

7. When the last data is received, the DTC completes the data transfer for the specified number of

bytes after loading the receive data to the RAM. In this case, the DTC does not clear the

RxRDY flag. It, however, clears the DTC enable register G (DTCEG). Accordingly, hereafter,

no transfer request will be issued to the DTC.

8. When the DTC transfer has been completed, an RxRDY interrupt (IERxI) is issued to the

CPU. In this interrupt handling routine, the RxRDY flag is cleared.

9. When the last data is received, a receive normal completion (RxF) interrupt (IERSI) occurs.

In this case, the CPU clears the RxF flag to complete the receive normal completion interrupt.

The MRQ flag is cleared to 0.

Notes: 1. As a receive status interrupt (IERSI), an receive error completion (RxE) interrupt as

well as the receive start detection (RxS) and receive normal completion (RxF)

interrupts must be enabled. If a receive error completion interrupt is disabled, no

interrupt is generated even if the reception is terminated by an error.

2. The interrupt occurs after the DTC transfer has been completed. Accordingly, the

interrupt described in item 8 actually occurs after item 9 above.

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