H8SSLASH2224 datasheet(624/1071 Pages) RENESAS

624 / 1071 page

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 538 of 982

REJ09B0054-0500

transfer request by IETxI is generated and the second byte data is written to the transmit

buffer.

5. Similarly, the above data field load and transmission operations are repeated.

6. The DTC completes the data transfer for the number of specified bytes when data to be

transmitted in the last byte is written to. At this time, the DTC does not clear the TxRDY flag.

It, however, clears bit DTCEG5 in the DTC enable register G (DTCERG) not to generate more

DTC transfer request.

7. A TxRDY interrupt (IETxI) is issued to the CPU when the DTC transfer is completed. In this

interrupt handling routine, the TxRDY flag can be cleared. However, since the TxRDY

interrupt will be generated again after the last byte transfer, the TxRDY flag remains set. (Note

that the LUEE bit should be cleared to 0 because an underrun error occurs to terminate the

transfer if the LUEE bit in IECTR is set to 1.) Note, however, that the TxRDY interrupt should

be disabled because the TxRDY interrupt is always generated.

8. After the last data transfer has been completed, a transmit normal completion (TxF) interrupt

occurs. In this case, the CPU clears the TxF flag and completes the normal completion

interrupt and clears the SRQ flag to 0.

Notes: 1. As a transmit status interrupt (IETSI), a transmit error termination (TxE) interrupt as

well as the transmit start detection (TxS) and transmit normal completion (TxF)

interrupts must be enabled. If a transmit error completion interrupt is disabled, no

interrupt is generated even if the transfer is terminated by an error.

2. If the control bits sent from the master unit is H'0, H'4, H'5, or H'6 in slave

transmission, the IEB automatically performs processing and the TxS and TxF flags are

not set.

H8S/2224 Scheda tecnica(PDF) 624 Page - Renesas Technology Corp