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H8S/2224 Scheda tecnica(PDF) 631 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 631 Page - Renesas Technology Corp |
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631 / 1071 page ![]() Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Rev. 5.00 Aug 08, 2006 page 545 of 982 REJ09B0054-0500 14.6.7 Notes on DTC Specification When transmit or receive data is transferred by the DTC, bit 5 (for transmission) or bit 6 (for reception) in DTCERG must be set by the bit manipulation instruction (such as BSET or BCLR). In this case, other bits (bits 7 and 4 to 0) in DTCERG must not be set to 1. 14.6.8 Error Handling in Transmission Figure 14.15 shows the operation when a timing error occurs. When a timing error occurs in data transmission (1), there is a possibility that the next data is already transferred to the transmit buffer by the DTC and the TxRDY flag that is the DTC initiation source is already cleared to 0 (2). In this case, if retransfer is performed, data remained in the transmit buffer (previous frame data) is transmitted as the first byte data of the data field (3). To avoid this error, in master transmission, the first byte data in the data field should be written to the transmit buffer by software instead of using the DTC. After that, data can be transferred by the DTC. In this case, the SAR (transfer source address) and CRA (transfer counter) should be specified as follows. • An address of the on-chip memory that stores the second byte data → SAR • The number of bytes specified by message length –1 → CRA S MA SA CF LF D1 S MA SA CF LF D2 D1 (1) (2) (3) IETSR Transmit error frame Timing error Legend: S: MA: SA: CF: LF: D1, D2, ...Dn-1, Dn: Data field Start bit, broadcast bit Master address field Slave address field Control field Message length field 1st byte data transferred by DTC 1st byte data transferred by DTC 2nd byte data transferred by DTC Retransfer frame TxRDY IETEF TTME Figure 14.15 Error Processing in Transfer |
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