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H8S/2224 Scheda tecnica(PDF) 633 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 633 Page - Renesas Technology Corp |
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633 / 1071 page ![]() Section 15 Serial Communication Interface (SCI) Rev. 5.00 Aug 08, 2006 page 547 of 982 REJ09B0054-0500 Section 15 Serial Communication Interface (SCI) This LSI has independent serial communication interfaces (SCIs). The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extended function. 15.1 Features • The number of on-chip channels H8S/2258 Group, H8S/2239 Group, H8S/2238 Group, and H8S/2237 Group: Four channels (channels 0, 1, 2, and 3) H8S/2227 Group: Three channels (channels 0, 1, and 3) • Choice of asynchronous or clocked synchronous serial communication mode • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. • On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). • Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) • Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error — that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can be used to activate the data transfer controller (DTC) or the direct memory access controller (DMAC) (H8S/2239 Group only). • Module stop mode can be set Asynchronous mode • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits |
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