H8SSLASH2224 datasheet(658/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 572 of 982

REJ09B0054-0500

Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the

maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N

settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in

Smart Card interface mode. In Smart Card interface mode, S (the number of base clock periods in

a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data

Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with

external clock input.

When the ABCS bit in SEMR_0 of SCI_0 is set to 1 in asynchronous mode, the maximum bit rate

is twice the value shown in tables 15.4 and 15.5 (valid for H8S/2239 Group only).

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)

Operating Frequency

φφφφ (MHz)

2.097152*

2.4576*

Bit Rate

(bps)*

Error

(%)

Error

(%)

Error

(%)

Error (%)

110

141 0.03

148 –0.04

174

–0.26

212

0.03

150

103 0.16

108 0.21

127

0.00

155

0.16

300

207 0.16

217 0.21

255

0.00

0.16

600

103 0.16

108 0.21

127

0.00

155

0.16

1200

0.16

–0.70

0.00

0.16

2400

0.16

1.14

0.00

0.16

4800

0.16

–2.48

0.00

–2.34

9600

—

–2.48

0.00

–2.34

19200

—

0.00

–2.34

31250

0.00

—

0.00

38400

—

0.00

—

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