H8SSLASH2224 datasheet(657/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 571 of 982

REJ09B0054-0500

15.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control

independently for each channel, different bit rates can be set for each channel. Table 15.2 shows

the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,

clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and

it can be read or written to by the CPU at all times.

Table 15.2 The Relationships between the N Setting in BRR and Bit Rate B

Communication

Mode

ABCS bit*

Bit Rate

Error

B =

× 2 2n−1 × (N + 1)

φ × 106

Error (%) = {

× 64 × 2 2n−1 × (N + 1)

−1 } × 100

φ × 106

Asynchronous

Mode

B =

× 2 2n−1 × (N + 1)

φ × 106

Error (%) = {

× 32 × 2 2n−1 × (N + 1)

−1 } × 100

φ × 106

Clocked

Synchronous

Mode



B =

× 2 2n−1 × (N + 1)

φ × 106



Smart Card

Interface Mode



B =

× 2 2n+1 × (N + 1)

φ × 106

Error (%) = {

× S × 2 2n+1 × (N + 1)

−1 } × 100

φ × 106

Legend:

Bit rate (bit/s)

BRR setting for baud rate generator (0

≤ N ≤ 255)

φ:

Operating frequency (MHz)

n and S: Determined by the SMR settings shown in the following tables.

Note:

* If the ABCS bit is set to 1, SCI_0 on the H8S/2239 Group only valid bit rate.

SMR Setting

CKS1

CKS0

Clock

Source

BCP1

BCP0

φ/4

φ/16

372

φ/64

256

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