H8SSLASH2224 datasheet(698/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 612 of 982

REJ09B0054-0500

state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/

E bit in

SMR to 1 to invert the parity bit for both transmission and reception.

15.7.3

Block Transfer Mode

Operation in block transfer mode is the same as that in the normal Smart Card interface mode,

except for the following points.

• In reception, though the parity check is performed, no error signal is output even if an error is

detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the

parity bit of the next frame.

• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the

start of the next frame.

• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu

after transmission start.

• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but

since error signal transfer is not performed, this flag is always cleared to 0.

15.7.4 Receive Data Sampling Timing and Reception Margin

In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can

only be used as a transmission/reception clock. In this mode, the SCI operates on a base clock with

a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal

asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the

falling edge of the start bit using the base clock, and performs internal synchronization. As shown

in figure 15.28, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th

pulse of the base clock, data can be latched at the middle of the bit. The reception margin is given

by the following formula.

M = | (0.5

−

)

− (L − 0.5) F −

+ F) | × 100%

| D

− 0.5 |

Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formula is as follows.

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