H8SSLASH2224 datasheet(700/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 614 of 982

REJ09B0054-0500

after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to

1. Whether SCI has finished transmission or not can be checked with the TEND flag.

15.7.6

Serial Data Transmission (Except for Block Transfer Mode)

As data transmission in Smart Card interface mode involves error signal sampling and

retransmission processing, the operations are different from those in normal serial communication

interface mode (except for block transfer mode). Figure 15.29 illustrates the retransfer operation

when the SCI is in transmit mode.

1. If an error signal is sent back from the receiving end after transmission of one frame is

complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next

parity bit is sampled.

2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality

is received. Data is retransferred from TDR to TSR, and retransmitted automatically.

3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

Transmission of one frame, including a retransfer, is judged to have been completed, and the

TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt

request is generated. Writing transmit data to TDR transfers the next transmit data.

Figure 15.31 shows a flowchart for transmission. A sequence of transmit operations can be

performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a

transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and

a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is

designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,

and transfer of the transmit data will be carried out. At this moment, if DISEL in DTC is 0 with

the transfer counter not being 0, the TDRE and TEND flags are automatically cleared to 0 when

data is transferred by the DTC. When DISEL is 1, or DISEL is 0 with the transfer counter being 0,

the DTC writes the transfer data to the TDR but does not clear the flag. Therefore, the flag should

be cleared by CPU. In addition, in the event of the error, the SCI retransmits the same data

automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not

activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes

in the event of an error, including retransmission. However, the ERS flag is not cleared

automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an

ERI request will be generated in the event of an error, and the ERS flag will be cleared.

When performing transfer using the DTC, it is essential to set and enable the DTC before carrying

out SCI setting. For details of the DTC setting procedures, refer to section 9, Data Transfer

Controller (DTC).

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