H8SSLASH2224 datasheet(750/1071 Pages) RENESAS

750 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 664 of 982

REJ09B0054-0500

Data 2

Data 3

Data 2

Data 1

[3]

[8]

[12]

Stop condition

generated

[4] IRTR = 0

Bit 6

Bit 5

Bit 4 Bit 3

Bit 2

Bit 1 Bit 0

Bit 0

1 clock cycle wait time

Bit 7

[4] IRTR = 1

[13] IRTR = 1

[13] IRTR = 0

[15] WAIT cleared to 0

IRIC clearance

[14] IRIC clearance

[11] IRIC clearance

[6] IRIC clearance

User processing

[10] ICDR read (data 2)

[16] ICDR read (data 3)

[9] TRS set to 1

[7] ACKB set to 1

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

[17] Stop condition

issued

Figure 16.13 Example of Master Receive Mode Stop Condition Generation Timing

(MLS = ACKB = 0, WAIT = 1)

16.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal.

The slave device compares its own address with the slave address in the first frame following the

establishment of the start condition issued by the master device. If the addresses match, the slave

device operates as the slave device designated by the master device.

Figure 16.14 is a flowchart showing an example of slave receive mode operation.

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