H8SSLASH2224 datasheet(747/1071 Pages) RENESAS

747 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 661 of 982

REJ09B0054-0500

Set WAIT = 1 (ICMR)

Clear IRIC flag in ICCR

Set ACKB = 0 (ICSR)

Set TRS = 0 (ICCR)

Read ICDR

Read IRIC flag in ICCR

IRIC = 1?

Yes

[1]

Set to receive mode

[2]

Receive start, dummy read.

[7]

Set acknowledge data for final receive.

[9]

Set TRS to generate stop condition.

[11] Clear IRIC flag (cancel wait state).

[16] Read final receive data.

[15] Cancel wait mode

Clear IRIC flag. (IRIC flag should be

cleared when WAIT = 0.)

[17] Generate stop condition.

[12] Wait for end of reception of 1 byte.

(IRIC set at rising edge of 9th clock cycle)

Clear IRIC flag in ICCR

Set ACKB = 1 (ICSR)

Set TRS = 1 (ICCR)

Read IRIC flag in ICCR

Set WAIT = 0 (ICMR)

Clear IRIC flag in ICCR

Read ICDR

IRIC = 1?

Write BBSY = 0

and SCP = 0 (ICCR)

End

Master receive mode

[3]

Receive wait state (IRIC set at falling edge

of 8th clock cycle)

Figure 16.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)

(Example)

The procedure for receiving data sequentially, using the wait states (WAIT bit) for

synchronization with ICDR (ICDRR) read operations, is described below.

The procedure below describes the operation for receiving multiple bytes. Note that some of the

steps are omitted when receiving only 1 byte. Refer to figure 16.11 for details.

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