H8SSLASH2224 datasheet(752/1071 Pages) RENESAS

752 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 666 of 982

REJ09B0054-0500

The reception procedure and operations in slave receive mode are described below.

[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR

according to the operating mode.

[2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set

to 1.

[3] When the slave address matches in the first frame following the start condition, the device

operates as the slave device specified by the master device. If the 8th data bit (R/

W) is 0, the

TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.

[4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an

acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in

ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has

been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag

has been set to 1, the slave device drives SCL low from the fall of the receive clock until data

is read into ICDR.

[5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Read the

IRDR flag and clear the IRIC flag to 0 consecutively, with no interrupt processing occurring

between them. If the time needed to transmit one byte of data elapses before the IRIC flag is

cleared, it will not be possible to determine when the transfer has completed.

Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is

changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in

ICCR is cleared to 0.

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