H8SSLASH2224 datasheet(748/1071 Pages) RENESAS

748 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 662 of 982

REJ09B0054-0500

[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the

ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the

WAIT bit in ICMR to 1.

[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,

and data received, in synchronization with the internal clock.

[3] The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request

is issued to the CPU if the IEIC bit in ICCR is set to 1.

(1) The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.

SCL is automatically held low, in synchronization with the internal clock, until the IRIC

flag is cleared.

(2) The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.

The IRTR flag is set to 1, indicating that reception of 1 frame of data has ended. The

master device continues to output the receive clock for the receive data.

[4] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by

clearing the IRIC flag as described in step [6] below. If the IRTR flag value is 1 and the next

receive data is the final receive data, perform the end processing described in step [7] below.

[5] If the IRTR flag value is 1, read the ICDR receive data.

[6] Clear the IRIC flag to 0. The reading of the ICDR flag described in step [5] and the clearing

of the IRIC flag to 0 should be performed consecutively, with no interrupt processing

occurring between them. During wait operation, clear the IRIC flag to 0 when the value of

counter BC2 to BC0 is 2 or greater. If the IRIC flag is cleared to 0 when the value of counter

BC2 to BC0 is 1 or 0, it will not be possible to determine when the transfer has completed. If

condition [3]-1 is true, the master device drives SDA to low level and returns an

acknowledge signal when the receive clock outputs the 9th clock cycle.

Further data can be received by repeating steps [3] through [6].

[7] Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive.

[8] Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge

of the 1st clock cycle of the next receive data.

[9] Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR

bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle

is input.

[10] Read the ICDR receive data.

[11] Clear the IRIC flag to 0. As in step [6], read the ICDR flag and clear the IRIC flag to 0

consecutively, with no interrupt processing occurring between them. During wait operation,

clear the IRIC flag to 0 when the value of counter BC2 to BC0 is 2 or greater.

[12] The IRIC flag is set to 1 by the following two conditions.

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