H8SSLASH2224 datasheet(762/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 676 of 982

REJ09B0054-0500

16.5

Interrupt Source

IICI is the interrupt source of IIC. Table 16.6 shows each interrupt source and its priority. The

ICCR interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt

controller.

Table 16.6 IIC Interrupt Source

Channel

Name

Enable Bit

Interrupt Source

Interrupt

Flag

Interrupt

Priority

IICI0

IEIC

2C bus interface interrupt

request

IRIC

High

IICI1

IEIC

2C bus interface interrupt

request

IRIC

Low

16.6

Usage Notes

1. In master mode, if an instruction to generate a start condition is issued and then an instruction

to generate a stop condition is issued before the start condition is output to the I2C bus, neither

condition will be output correctly. To output the start condition followed by the stop condition,

after issuing the instruction that generates the start condition, read PORT in each I2C bus

output pin, and check that SCL and SDA are both low. Even if the ICE bit is set to 1, it is

possible to monitor the pin state by reading the PORT register so long as the DDR I/O port

generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared

to 0.

2. Either of the following two conditions will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from

ICDRT to ICDRS)

 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from

ICDRS to ICDRR)

3. Table 16.7 shows the timing of SCL and SDA output in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

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