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H8S/2224 Scheda tecnica(PDF) 786 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 786 Page - Renesas Technology Corp |
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786 / 1071 page ![]() Section 17 A/D Converter Rev. 5.00 Aug 08, 2006 page 700 of 982 REJ09B0054-0500 (1) (2) tD tSPL tCONV φ Address Write signal Input sampling timing ADF Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 17.5 A/D Conversion Timing Table 17.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay tD 18 — 33 10 — 17 6 — 9 4 — 5 Input sampling time tSPL — 127 — — 63 — — 31 — — 15 — A/D conversion time tCONV 515 — 530 259 — 266 131 — 134 67 — 68 Note: All values represent the number of states. Table 17.4 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 512 (Fixed) 0 1 256 (Fixed) 0 128 (Fixed) 1 1 64 (Fixed) |
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