H8SSLASH2224 datasheet(827/1071 Pages) RENESAS

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Section 20 Flash Memory (F-ZTAT Version)

Rev. 5.00 Aug 08, 2006 page 741 of 982

REJ09B0054-0500

Erase start

Set EBR1 (2)

Enable WDT

Disable WDT

Read verify data

Increment address

Verify data = all 1?

Last address of block?

All erase block erased?

Set block start address as verify address

H'FF dummy write to verify address

SWE1 bit in FLMCR1

← 1

= 1

ESU1 bit in FLMCR1

← 1

E1 bit in FLMCR1

← 1

start erasing

stop erasing

tsswe: Wait 1

µs

tsswe: Wait 100

µs

E1 bit in FLMCR1

← 0

EV1 bit in FLMCR

← 1

tse: Wait 10 ms

ESU1 bit in FLMCR1

← 0

tce: Wait 10

µs

tcesu: Wait 10

µs

tsev: Wait 20

µs

EV1 bit in FLMCR

← 0

← n + 1

tcer: Wait 4

µs

SWE1 bit in FLMCR1

← 0

tcswe: Wait 100

µs

EV1 bit in FLMCR

← 0

≥ 100?*5

tcer: Wait 4

µs

SWE1 bit in FLMCR1

← 0

tcswe: Wait 100

µs

Erase failure

End of erasing

tsevr: Wait 2

µs

Yes

Erasing should be

done to a block

1. Pre-writing (all erase block data are cleared to 0) is not necessary.

2. Verify data is read out in 16 bit size (word access).

3. Erasing block register (EBR) can be set about 1 bit at a time.

Do not specify 2 bits or more.

4. Erasing is performed block by block. When multiple blocks must be erased,

erase each lock one by one.

5. This is a recommended value. To change it, consult tables 27.12, 27.25, 27.37, 27.49, and 27.59 and select

a new value such that the erase time (tE), wait time after E1 bit setting (tse), and maximum erase count (N)

do not exceed the maximum values indicated.

Notes:

Figure 20.12 Erase/Erase-Verify Flowchart

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