H8SSLASH2224 datasheet(826/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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Section 20 Flash Memory (F-ZTAT Version)

Rev. 5.00 Aug 08, 2006 page 740 of 982

REJ09B0054-0500

20.8.2

Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.12 should be

followed.

1. Prewriting (setting erase block data to all 0) is not necessary.

2. Erasing is performed in block units. Make only a single-bit specification in the erase block

turn.

3. The time during which the E1 bit is set to 1 is the flash memory erase time.

4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (tsesu + tse + tce + tcesu) ms as the WDT overflow period.

5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit

are B'0. Verify data can be read in words from the address to which a dummy write was

performed.

5. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-

verify sequence as before. The maximum number of repetitions of the erase/erase-verify

sequence is (N).

H8S/2224 Scheda tecnica(PDF) 826 Page - Renesas Technology Corp