H8SSLASH2224 datasheet(865/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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865 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 779 of 982

REJ09B0054-0500

23.3

Duty Adjustment Circuit

The duty adjustment circuit is valid when oscillation frequency is more than 5 MHz. The duty

adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system

clock (

φ).

23.4

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate

φ/2, φ/4, φ/8, φ/16, and φ/32.

23.5

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the clock supplied to the bus master by setting the

bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from system clock (

φ), or

medium-speed clocks (

φ/2, φ/4, φ/8, φ/16, φ/32).

23.6

System Clock when Using IEBus

When using the IEBus, the system clock must be set to either 12 MHz or 12.58 MHz. When the

IEBus is not used, the system clock can be set to an arbitrary frequency between 10 MHz to 13.5

MHz.

Note: IEBus is supported only by the H8S/2258 Group.

H8S/2224 Scheda tecnica(PDF) 865 Page - Renesas Technology Corp